module rs_trigger(clk, r, s, q, rst);
input clk, r, s,rst;
output q;
reg q;

always@(posedge clk) begin
	if (rst)
		q = 0;
	else
		case({r,s})
		2'b00: q = q;
		2'b01: q = 1'b0;
		2'b10: q = 1'b1;
		default: q = q;
		endcase
end

endmodule
